View SY58608UMG_754785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SY58608U
3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input
General Description
The SY58608U is a 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two identical output copies with less than 20ps of skew and less than 10psPP total jitter. The SY58608U can process clock signals as fast as 2GHz or data patterns up to 3.2Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mVPP) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated voltage reference (VREF-AC) is provided to bias the VT pin. The outputs are 325mV LVDS, with rise/fall times guaranteed to be less than 100ps. The SY58608U operates from a 2.5V 5% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require CML or LVPECL outputs, consider Micrel's SY58606U and SY58607U, 1:2 fanout buffers with 400mV and 800mV output swings respectively. The SY58608U is part of (R) Micrel's high-speed, Precision Edge product line. Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* Precision 1:2, 325mV LVDS fanout buffer * Guaranteed AC performance over temperature and voltage: - DC-to > 3.2Gbps throughput - <300ps propagation delay (IN-to-Q) - <20ps within-device skew - <100ps rise/fall times * Fail Safe Input - Prevents outputs from oscillating when input is invalid * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * High-speed LVDS outputs * 2.5V 5% power supply operation * Industrial temperature range: -40C to +85C (R) * Available in 16-pin (3mm x 3mm) MLF package
Functional Block Diagram
Applications
* * * * All SONET clock and data distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution Backplane distribution
Markets
* * * * * DataCom Telecom Storage ATE Test and Measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
October 2006
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Ordering Information(1)
Part Number SY58608UMG SY58608UMGTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
(2)
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 608U with Pb-Free bar-line indicator 608U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
16-Pin MLF (MLF-16)
(R)
Pin Description
Pin Number 1, 4 Pin Name IN, /IN Pin Function Differential Inputs: This input pair is the differential signal input to the device. Input accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of this pair internally terminates with 50 to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the outputs to its last valid state. See "Input Interface Applications" section for more details. Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See "Input Interface Applications" section. Reference Voltage: This output bias to VCC-1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. See "Input Interface Applications" section for more details. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. LVDS Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 325mV. Normally terminated 100 across the output pairs (Q and /Q). See "LVDS Output Termination" section.
2
VT
3
VREF-AC
5, 8,13, 16 6, 7, 14, 15 9, 10 11, 12
VCC GND, Exposed pad /Q1, Q1 /Q0, Q0
October 2006
2
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. -0.5V to +4.0V Input Voltage (VIN) .............................. -0.5V to VCC +0.3V LVDS Output Current (IOUT) ................................... 10mA Input Current Source or Sink Current on (IN, /IN)................. 50mA Current (VREF) (4) Source or sink current on VREF-AC ............... 1.5mA Maximum Operating Junction Temperature............125C Lead Temperature (soldering, 20sec.) ....................260C Storage Temperature (Ts) ...................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VIN) ........................ +2.375V to +2.635V Ambient Temperature (TA) ..................... -40C to +85C (3) Package Thermal Resistance (R) MLF Still-air (JA) ............................................. 60C/W Junction-to-board (JB) ........................... 33C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC IN to VT
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating.
Parameter Power Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI Output Reference Voltage Voltage from Input to VT
Condition No load, max. VCC
Min 2.375
Typ 2.5 55
Max 2.625 75 110 VCC VIH-0.1 1.7
Units V mA V V V V
90 IN, /IN IN, /IN see Figure 3a, Note 6 see Figure 3b 1.2 0 0.1 0.2
100
30 VCC-1.3 VCC-1.2
100 VCC-1.1 1.28
mV V V
October 2006
3
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
LVDS Outputs DC Electrical Characteristics(7)
VCC = +2.5V 5%, RL = 100 across the output pairs; TA = -40C to +85C, unless otherwise stated.
Symbol VOUT VDIFF_OUT VOCM VOCM
Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output Voltage Swing Differential Output Voltage Swing Output Common Mode Voltage Change in Common Mode Voltage
Condition See Figure 3a See Figure 3b
Min 250 500 1.125 -50
Typ 325 650 1.20
Max
Units mV mV
1.275 50
V mV
October 2006
4
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
AC Electrical Characteristics(8)
VCC = +2.5V 5%, RL = 100 across the output pairs, Input tr/tf: 300ps; TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD tSkew Parameter Maximum Frequency Propagation Delay Within Device Skew Part-to-Part Skew tJitter Data Clock tr, tf Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Time (20% to 80%) Duty Cycle
Notes: 8. 9. These high-speed parameters are Guaranteed by design and characterization. Within-device skew is measured between two different outputs under identical input transitions.
Condition NRZ Data VOUT > 200mV IN-to-Q VIN: 100mV-200mV VIN: 200mV-800mV Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing. Differential I/O Clock
Min 3.2 2 170 130
Typ 4.25 3 280 200 5
Max
Units Gbps GHz
420 300 20 135 1 10 1 10
ps ps ps ps psRMS psPP psRMS psPP ps %
35 47
60
100 53
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. 11. Random jitter is measured with a K28.7 pattern, measured at fMAX. 12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 13. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value.
12 23
October 2006
5
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing such that the differential voltage across the input pair is less than 100mV, the FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no indeterminate state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a differential voltage 100mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Characteristics" for detailed information.
Functional Description
Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of SY58608U is limited by the FSI function.
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
October 2006
6
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Typical Characteristics
VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100 across the output pairs, TA = 25C, unless otherwise stated.
October 2006
7
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 250mV, Data Pattern: 2 -1, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
23
October 2006
8
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Functional Characteristics (continued)
VCC = 2.5V, GND = 0V, VIN = 250mV, RL = 100 across the outputs, TA = 25C, unless otherwise stated.
October 2006
9
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Input Stage
Figure 2. Simplified Differential Input Buffer
Figure 3a. Single-Ended Swing
Figure 3c. LVDS Differential Measurement
Figure 3b. Differential Swing
Figure 3d. LVDS Common Mode Measurement
October 2006
10
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled)
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface (DC-Coupled)
Related Product and Support Documents
Part Number SY58606U Function 4.25Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input 3.2Gbps Precision, 1:2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input New Products and Termination Application Notes Data Sheet Link http://www.micrel.com/page.do?page=/productinfo/products/sy58606u.shtml http://www.micrel.com/page.do?page=/productinfo/products/sy58607u.shtml http://www.micrel.com/product-info/products/sy89830u.shtml
SY58607U
HBW Solutions
October 2006
11
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58608U
Package Information
16-Pin (3mm x 3mm) MLF (MLF-16)
(R)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
October 2006
12
M9999-102706-A hbwhelp@micrel.com or (408) 955-1690

▲Up To Search▲

Price & Availability of SY58608UMG

	To Download SY58608UMG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .